OLED-TV|Laser-TV|SED|Display|FED|

The typical goal of the FED designer is to prohibit the
electrons from striking any other surface other than the anode
after the electrons leave the emitters.
The SED emitter includes a multiple-scattering process.
Secondly, typical FEDs are voltage-drive devices. In a passive
matrix FED display, it is diffi cult to apply more than two or three
voltage levels between the cathode and the gate (ON and OFF
voltages), so gray scale in the image is achieved by pulse width
modulation (PWM). As for all passive matrix flat-panel displays, the image is created line-by-line. Asone line is activated, the pixels in that line are switched ON by the column drivers; the period that each pixel in the line is left ON is determined by the luminous intensity required from that pixel for that image frame.

Since the emission current from the emitters is highly nonlinear and the fabrication of the emitters is difficult to control, emission
uniformity and thus image uniformity are the major problems to
overcome for microtip and CNT displays. Fabrication techniques
have improved the uniformity of CNT-based FEDs. Often, emission
uniformity across the cathode is controlled by a current feedback
resistor placed in line with the cathode electrode.
Fabrication of FED emitter is a dependant of the approach taken
by the FED development team.
Motorola and LETI have developed processes that require CNT growth directly on the cathode substrate, while groups like ANI and Samsung have developed processes that allow printing of the CNT.

Printing approaches are more favorable for fabricating large area
cathodes with uniform emission in high volume as opposed to
high-temperature chemical vapor deposition (CVD) approaches
required for direct CNT growth.

The printing approaches require an activation step, but even this
has been optimized for large-area fabrication using a bead-blasting technique.SED structure—This is unique to other FED approaches, in that the electron beam current supplied to the anode for each pixel is generated in a two-step process.
In the first step, the electron source operates by first emitting
electrons laterally (parallel to the cathode substrate) across a very narrow gap formed between two electrodes. The gap between the electrodes, although small (on the order of a few nanometers), is still a vacuum gap that requires application of an electric potential to extract electrons from one electrode through the vacuum tunneling barrier to the other electrode. The current across the electrode gap follows the Fowler- Nordheim law and is thus highly nonlinear, allowing for matrix addressability. This lateral emitter structure is where the term surface conduction emitter (SCE) comes from.

Figure 6 is a diagram of the SED emitter structure.
In the second step, the electrons that tunnel across the gap
and strike the counter-electrode are either absorbed into the
counter-electrode (thereby creating only heat and no light) or
scattered, captured by the electric field created by the anode
potential and accelerated to a particular phosphor dot. Thus,
it creates a spot of red, green or blue light. This combined electron emission plus electron beam scattering process is illustrated in Figure 7, where Va is the anode potential and Vf is the driving potential across the gap. Multiple scattering events may take place before the electron is captured by the anode field. The effi ciency of the number of electrons captured by the anode field (Ie/If, Figure 7) is quite low, on the order of 3 percent, but the power efficiency is reasonable since Vf is low, on order of 20V. Note also that the uniformity of electron current reaching that anode depends on field emission current at the gap convoluted with the efficiency of scattering events from pixelto- pixel.

The emitter described in Figure 7 is fabricated using a combination
of technologies. The simple matrix wires are deposited by
a printing method using silver wires and insulating films at the
crossovers. Platinum (Pt) electrodes are formed using thin-film
lithography. The gap between these electrodes is 60m. The
carbon nano gap is created in a two-step process, beginning
by depositing a palladium oxide (PdO) film (10nm thick) by ink-jet
printing over and between the Pt electrodes. This film is composed of ultrafine particles of PdO of diameter about 10nm. First, a gap is “formed” in this film by reducing the oxide by passing a series of voltage pulses across this PdO film between the two Pt electrodes.

The PdO is reduced by the heat of the pulses as the substrate is
in a vacuum environment. As the PdO is reduced, the film is stressed and eventually a sub-micron gap is formed across the diameter of the PdO dot. Second, the gap is “activated” by exposing the cathode to an organic gas, and more pulse voltages are applied across the gap. These pulse voltages create a local discharge that leads to CVD-like deposition of a carbon film in the gap, such that the gap narrows to a self-limiting distance of order 5nm. When the gap is large, carbon material is deposited as a result of the disassociation of the hydrocarbon molecules in the plasma resulting from the discharge. As the gap becomes smaller, the local discharge current created by the pulse becomes large and material is evaporated.
At a gap of about 5nm, deposition and evaporation of carbon
material reaches equilibrium. The width of this gap is controlled by
the pressure of the organic gas and the pulse voltage. A cross
section image of this gap is shown in Figure 8.

Similar to the FED, the SED is driven line-by-line (Figure 9). The
scanning circuit generates the scan signal (Vscan), and the signal
modulation circuit generates a PWM signal (Vsig) that is synchronized with Vscan. Because of the highly nonlinear Ie-If characteristics of the surface conduction emitter, it is possible to drive each pixel selectively using a simple matrix x-y configuration without active elements and still achievea luminance contrast ratio of 100,000:1 with a signal voltage of 18.9V and a scanning voltage of 9.5V. Contrast these values with a typical signal voltage of 35-50V and scanning voltage of 50-100V for CNT-based FED structures. The SED switching devices are much lower voltage, but they must be designed for much higher steadystate current loads, as much as a factor of 30 or higher as a result of the inefficiency of the SCE electron scattering mechanism. The larger currents of the SED also forces the interconnect lines to have lower resistances compared with FED, as even a small voltage drop along the line can result in edge-to-edge non-uniformity.
The paper was originally presented at ASIA DISPLAY 2007 and is published courtesy of the Society of Information Displays.
By Richard Fink
VP of Engineering
E-mail: dfink@appliednanotech.net

Figure 5: The current from the emitter as a function of the applied voltageis highly nonlinear. Cesium lowers the workfunction and allows emission at lower extraction fields.

Figure 7: The electrons that tunnel across the gap and strike the counter-electrode are either absorbed into the counter-electrode or scattered, captured by the electric field created by the anode potential and accelerated to a particular phosphor dot.

Figure 9: The SED is driven line-by-line.

Figure 8: Shown is the SEM cross section image of the carbon nano gap fabricated by the forming and activation processes (a).The substrate deterioration is a result of the high temperature created locally by the activation process (b).